The deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade the performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, contact resistance becomes more significant and needs to be reduced.
The principle way of reducing the contact resistance between polysilicon gates and source/drain regions and interconnect lines is to form metal silicides atop the source/drain regions and the gate electrodes. Silicide regions are typically formed by a salicide (self-aligned silicide) process. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate, specifically over exposed source/drain and gate electrode regions. The wafer is then subjected to one or more annealing steps. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrode, thereby forming a metal silicide. The process is referred to as a self-aligned silicidation process because the silicide layer is formed only where the metal material directly contacts the silicon source/drain regions and the polycrystalline silicon (polysilicon) gate electrode. Following the formation of the silicide layer, the un-reacted metal is removed.
The conventional silicide formation processes suffer drawbacks. For example, in the formation of NMOS devices, due to a high arsenic concentration in the source/drain regions, nickel silicide often encroaches under spacers. As a result, the distance between the silicide regions and the respective source/drain junctions is reduced. The distances are particularly smaller in lightly-doped source/drain regions due to their shallow junctions. Leakage currents are thus increased. In the formation of PMOS devices, on the other hand, the source/drain regions are often formed of SiGe. It has been found that the silicide regions formed on SiGe often have greater roughness due to non-uniform SiGe formation. Also, the thickness of the silicide regions varies significantly. For integrated circuits with shallow junctions, the thickness variation of the silicide regions causes a degradation in the performance of the MOS devices. Therefore, new silicide formation methods are needed.